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Layout Engineer

The Programme 

台积公司成立于1987年,率先开创了专业集成电路制造服务之商业模式,自此成为全球规模专业集成电路制造服务公司。台积公司以领先业界的制程技术及设计解决方案组合支持其客户及伙伴生态系统的蓬勃发展,以此释放全球半导体产业的创新。身为全球的企业公民,台积公司的营运范围遍及亚洲、欧洲及北美,致力成为企业社会责任的行动者。 

Responsibilities 

  • Full layout design for std cell/IO/SRAM IPs in advanced node 
  • Work on the physical verification(DRC/LVS/Antenna ...) 
  • Work on test chip layout design and verification
  • Close cooperation with designers on PPA optimization  

Required Skills and Abilities 

  • At least BS Degree of Microelectronics or Physics 
  • Excellent graduate or at least 1 years' related working experience 
  • Familiar with layout design and verification tools(Virtuoso,Laker,Calibre) 
  • Familiar with design rule and layout effect in advanced process. 
  • Excellent skills of communication and teamwork are also expected. 
  • Programming experience(perl/tcl skill) will be a plus. 
  • Experience in advanced process (n16 and beyond) will be a plus. 
     
Closed 5 days ago
Closed 5 days ago
  • Job type:Graduate Jobs
  • Disciplines:

    Engineering

  • Citizenships:

  • Locations:

    Nanjing (China)

  • Closing Date:8th May 2021, 6:00 pm

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